IBM Announces 5nm Chip With 30 Billion Transistors

IBM Announces 5nm Chip With 30 Billion Transistors

IBM believes this new process won't cost any more than chips with today's transistor designs, but its approach requires the use of extreme ultraviolet light to etch chip features onto silicon wafers. Nearly two years back, they created a 7nm test node with 20 billion transistors using the same approach.

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Back in 2015 the company demonstrated the world's first FinFET chip based on a 7nm process, and now the company claims to have a means of producing the industry's first parts based on a 5nm process node.

IBM has teamed up with semiconductor equipment suppliers and manufacturing bigwigs GlobalFoundries and Samsung to develop a new process for building silicon nanosheet transistors.

IBM, along with its Research Alliance partners, has developed a new 5nm chip that boosts the performance up to 40% at the same power when compared to the 10nm chips now available in the market. The process still uses EUV lithography, but beats the 7nm FinFET test node offering 20 billion transistors by packing up to 30 billion transistors in the same area. In some background information to the development, we are told that IBM has been exploring nanosheet semiconductor technology for more than 10 years.

The smallest and most advanced chips currently commercially available are made up of transistors with gates about 10 nm long, but IBM has now unveiled plans to cut them in half. By halving the size but increasing performance and energy efficiency, IBM's 5 nm chips has the potential to push the consumer electronics market forward, especially the IoT and even the smartphone markets, at an accelerated pace.

For practical purposes, this is important because it helps enable a 40 percent performance improvement over current 10nm chip designs - but using the same amount of power.

These stacks of nanosheets were used as the device structure of the transistor, instead of the standard architecture. Beside the shorter wavelength advantage of EUV, the Research Alliance also found ways to continuously adjust the width of its nanosheets in both the chip design and manufacturing process phases. "This adjustability permits the fine-tuning of performance and power for specific circuits - something not possible with today's FinFET transistor architecture production", says IBM. It can be used but merely reducing the space between the fins won't increase the current flow and eventually the performance. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3-D chip stacking and Air gap insulators.

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